Constraining Designs for Synthesis and Timing Analysis by Sridhar Gangadharan & Sanjay Churiwala
Author:Sridhar Gangadharan & Sanjay Churiwala
Language: eng
Format: epub
Publisher: Springer New York, New York, NY
Both the launching device (outside the block of interest) and the capture device (inside the block of interest) will have similar latencies on the clock path. The timing analysis tool is anyways going to consider the clock within the block of interest. These switches only impact the clock edge on the launching side. It is always much easier and intuitive if both sides are treated similarly. Specifying these switches cause a different treatment on the launch side which is not very intuitive.
It is much more intuitive to comprehend the delay from the launching device till the destination, rather than going further down the clock source also.
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Computer Design | Control Systems |
DSPs | Embedded Systems |
Microprocessor Design | PIC Microcontroller |
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